Field Programmable Gate Array

A 12 Gbps DES Encryptor/Decryptor Core in an FPGA

Software Development / Encryption / Field Programmable Gate Array / High Speed / Data Encryption Standard

Improving utilization of reconfigurable resources using two dimensional compaction

Distributed Computing / Resource use / Real Time Systems / The / Field Programmable Gate Array / Task Allocation / Partial Reconfiguration / System performance / Task Allocation / Partial Reconfiguration / System performance

A 12 Gbps DES Encryptor/Decryptor Core in an FPGA

Software Development / Encryption / Field Programmable Gate Array / High Speed / Data Encryption Standard

Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine

Information Systems / Genetic Algorithms / Field-Programmable Gate Arrays / Genetic Algorithm / System Architecture / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route

A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine

Information Systems / Genetic Algorithms / Field-Programmable Gate Arrays / Genetic Algorithm / System Architecture / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route

Improving utilization of reconfigurable resources using two-dimensional compaction

Distributed Computing / Resource use / Real Time Systems / The / Field Programmable Gate Array / Task Allocation / Partial Reconfiguration / System performance / Task Allocation / Partial Reconfiguration / System performance

Application specific programmable IP core for motion estimation: Technology comparison targeting efficient embedded co-processing units

Performance Analysis / Motion estimation / Digital System Design / Field Programmable Gate Array / Real Time / High performance / Embedded System / Application Specific Integrated Circuit (ASIC) / High performance / Embedded System / Application Specific Integrated Circuit (ASIC)

EFFICIENT SIGNAL PROCESSING USING SYNTACTIC PATTERN RECOGNITION METHODS

Signal Processing / Hardware Design / Signal and Image Processing / Syntactic Pattern Recognition / Field Programmable Gate Array / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms

EFFICIENT SIGNAL PROCESSING USING SYNTACTIC PATTERN RECOGNITION METHODS

Signal Processing / Hardware Design / Signal and Image Processing / Syntactic Pattern Recognition / Field Programmable Gate Array / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms

A multiprocessor self-reconfigurable JPEG2000 encoder

Computer Architecture / Field-Programmable Gate Arrays / Processor Architecture / Hardware / Field Programmable Gate Array / JPEG / IPDPS / Multi-threading / Embedded System / Dynamic Reconfiguration / JPEG / IPDPS / Multi-threading / Embedded System / Dynamic Reconfiguration

FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications

Case Study / Field Programmable Gate Array / Fuzzy Logic and Its Application / Circuit Design / Radar Cross Section / Generic model

RFnest™: Radio frequency network emulator simulator tool

Model validation / Impulse response / Radio Frequency / Field Programmable Gate Array / Real Time / Virtual Networks / Network Emulation / Front end / Modular Design / Network Simulator / Simulation Tool / Channel Impulse Response (CIR) / Wireless Communication / Virtual Networks / Network Emulation / Front end / Modular Design / Network Simulator / Simulation Tool / Channel Impulse Response (CIR) / Wireless Communication

Dynamic partial self-reconfiguration on spartan-III FPGAs via a parallel configuration access port (PCAP)

FPGA Architecture and CAD / Field Programmable Gate Array / Embedded processor / Partial Reconfiguration

Self-reconfiguration on Spartan-III FPGAs with compressed partial bitstreams via a parallel configuration access port (cPCAP) core

FPGA Architecture and CAD / Field Programmable Gate Array / Embedded processor

Field Programmable Compressor Trees

Signal Processing / Computer Hardware / Field Programmable Gate Array / High performance

A Custom-made Algorithm-Specific Processor for Model Predictive Control

Model Predictive Control / Field Programmable Gate Array

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